In the advancement of electronic VLSI industry, it focuses mainly on the Power, Area and Delay, by this the Ternary Logic system is an efficient than the binary logic. The Ternary logic that minimizes the complexity, interconnections and higher operating speeds of the circuit compared to binary logic system. The ternary logic system is a multi-valued logic has its base as 3 i.e., the three logic levels are 0, 1, 2. For this the CNFET is chosen regarding the ternary circuit design, by altering the CNFET transistor’s diameter, it can provide a range of threshold voltages. The Ternary Full Adder represented in this work is made up of Unary Operators, Ternary Multiplexer and Capacitive Threshold Logic circuit and to reduce the number of transistors and energy consumption, the circuit uses two distinct voltages, Vdd and Vdd/2. The proposed circuit is an efficient one, it achieves a 21.9% reduction in power consumption and a 16.7% improvement in delay. The designed circuit is simulated using Cadence virtuoso and Stanford 32 nm CNFET Technology. The Simulation result shows improvement in the reduction of the power consumption and delay reduction of the circuit.