Cloud computing biggest challenge nowadays is data hacking; therefore, data encryption is one of several ways to secure data. Encryption uses a key to encode data so only authorised users can view it. A simple, energy- and space-efficient endurance approach for secure resistive main memory is presented in this study. This approach uses the random properties of AES-encrypted data with a rotating shift operation. Random Shifter is energy-efficient and hardware-easy. This approach is much smaller than others presented previously. Secure memory using random shifter and other error correcting techniques. Rand Shifter uses less power than Barrel Shifter, Row Verifier, Checker, & Multipliers. Designing a System on Chip AES with The pipeline and Random shifter enhances this paper. Reduce power and delay when compared with AES without pipelining. Overview, definition of the issue, pipeline lining AES, and result were covered in this study. This paper uses model sim & Xilinx 14.5. This project is useful for communication, networking, memory device data protection, Wi-Fi (WPA2), mobile applications, native processing support, libraries in various software programming languages, VPN implementations, and mobile apps.

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Design of FPGA Based High Security Data Transmission System Using 256-Bit Cryptography Algorithm

  • Gollamandala Rajesh,
  • Kota Venkanna

摘要

Cloud computing biggest challenge nowadays is data hacking; therefore, data encryption is one of several ways to secure data. Encryption uses a key to encode data so only authorised users can view it. A simple, energy- and space-efficient endurance approach for secure resistive main memory is presented in this study. This approach uses the random properties of AES-encrypted data with a rotating shift operation. Random Shifter is energy-efficient and hardware-easy. This approach is much smaller than others presented previously. Secure memory using random shifter and other error correcting techniques. Rand Shifter uses less power than Barrel Shifter, Row Verifier, Checker, & Multipliers. Designing a System on Chip AES with The pipeline and Random shifter enhances this paper. Reduce power and delay when compared with AES without pipelining. Overview, definition of the issue, pipeline lining AES, and result were covered in this study. This paper uses model sim & Xilinx 14.5. This project is useful for communication, networking, memory device data protection, Wi-Fi (WPA2), mobile applications, native processing support, libraries in various software programming languages, VPN implementations, and mobile apps.