Deep Neural Networks (DNNs) have become a fundamental computing paradigm employed in a plethora of applications, from edge devices to space exploration. As DNNs are increasingly used on applications that demand high reliability, understanding their tolerance to hardware faults is mandatory. In this chapter, we review how abstract faults can impact various DNNs, including investigating the impact of different numerical formats and fault models. We then focus on two different hardware implementations. First, Graphics Processing Units (GPUs), which are today’s workhorse for AI applications, providing enormous compute capacity and the flexibility to execute the most advanced networks. Then we study, architectures based on Non-volatile Memories (eNVMs), which are extremely low power, but the size of the networks that they can process is limited due to the intrinsic variability of the memory devices. We show that some of the insights extracted from experiments with abstract networks apply to both hardware implementations, while each one has its own specificities.

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Understanding Neural Network Fault Tolerance: From Analog Hardware to the GPU

  • Adrian Evans,
  • Manon Dampfhoffer,
  • Stéphane Burel,
  • Fernando Fernandes dos Santos,
  • Joel Minguet Lopez

摘要

Deep Neural Networks (DNNs) have become a fundamental computing paradigm employed in a plethora of applications, from edge devices to space exploration. As DNNs are increasingly used on applications that demand high reliability, understanding their tolerance to hardware faults is mandatory. In this chapter, we review how abstract faults can impact various DNNs, including investigating the impact of different numerical formats and fault models. We then focus on two different hardware implementations. First, Graphics Processing Units (GPUs), which are today’s workhorse for AI applications, providing enormous compute capacity and the flexibility to execute the most advanced networks. Then we study, architectures based on Non-volatile Memories (eNVMs), which are extremely low power, but the size of the networks that they can process is limited due to the intrinsic variability of the memory devices. We show that some of the insights extracted from experiments with abstract networks apply to both hardware implementations, while each one has its own specificities.