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The Matrix-Vector Multiplication (MVM) is a widespread operation in Neural Network inference. Analog in-Memory Computing (AiMC) allows to compute MVMs directly inside the memory unit, reducing data transfer overhead. This paper explores two well-known architectures to perform signed-MVMs showing a trade-off between computational throughput and array size. Moreover, a topology based on an analog Current Subtractor (CS), potentially beneficial for computational energy efficiency, is analyzed. The CS is designed and simulated in a NCSU FreePDK 45-nm CMOS process, and achieves a \(2.35\%\) average MVM output error, compared with the ideal MVM execution.

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Current Subtraction for Signed MVM Analog in-Memory Computation on Resistive Arrays

  • 会议论文

  • 发表日期：

    2026年

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  • Lorenzo Greco,
  • Andrea Lico,
  • Fatima Gahem,
  • Eleonora Franchi Scarselli,
  • Marco Pasotti,
  • Alessio Antolini

摘要

The Matrix-Vector Multiplication (MVM) is a widespread operation in Neural Network inference. Analog in-Memory Computing (AiMC) allows to compute MVMs directly inside the memory unit, reducing data transfer overhead. This paper explores two well-known architectures to perform signed-MVMs showing a trade-off between computational throughput and array size. Moreover, a topology based on an analog Current Subtractor (CS), potentially beneficial for computational energy efficiency, is analyzed. The CS is designed and simulated in a NCSU FreePDK 45-nm CMOS process, and achieves a \(2.35\%\) average MVM output error, compared with the ideal MVM execution.