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As real-time Artificial Intelligence (AI) applications on edge devices continue to grow, Field Programmable Gate Array (FPGA)-based Convolutional Neural Network (CNN) accelerators are increasingly adopted for their configurability and energy efficiency. However, timing variability introduced by memory access latency, refresh cycles, and bus contention poses significant verification challenges. This article presents a Verification IP (VIP) core designed to monitor and validate the unit responsible for data flow control in such accelerators. The VIP has been applied to the Scheduler block of FPG-AI, a flexible framework developed at the University of Pisa to generate custom HDL for deploying CNNs on FPGA-based System-on-Chips (SoCs). Implemented using SystemVerilog and the Universal Verification Methodology (UVM), the VIP employs constrained-random testing and transaction-level modeling to assess functional correctness under variable conditions. A reference model and scoreboard enable comprehensive and accurate output checking. Validation tests based on the LeNet model, using randomized inference patterns, demonstrate the VIP’s effectiveness and high coverage. This work establishes a reusable and scalable verification strategy for FPGA-based CNN accelerators in edge AI deployments, emphasizing the importance of robust hardware validation.

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UVM-Based Verification of a Configurable Data Flow-Control IP Core for FPGA CNN Accelerators

  • 会议论文

  • 发表日期：

    2026年

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  • Angelo Paone,
  • Tommaso Pacini,
  • Luca Zulberti,
  • Pietro Nannipieri,
  • Luca Fanucci

摘要

As real-time Artificial Intelligence (AI) applications on edge devices continue to grow, Field Programmable Gate Array (FPGA)-based Convolutional Neural Network (CNN) accelerators are increasingly adopted for their configurability and energy efficiency. However, timing variability introduced by memory access latency, refresh cycles, and bus contention poses significant verification challenges. This article presents a Verification IP (VIP) core designed to monitor and validate the unit responsible for data flow control in such accelerators. The VIP has been applied to the Scheduler block of FPG-AI, a flexible framework developed at the University of Pisa to generate custom HDL for deploying CNNs on FPGA-based System-on-Chips (SoCs). Implemented using SystemVerilog and the Universal Verification Methodology (UVM), the VIP employs constrained-random testing and transaction-level modeling to assess functional correctness under variable conditions. A reference model and scoreboard enable comprehensive and accurate output checking. Validation tests based on the LeNet model, using randomized inference patterns, demonstrate the VIP’s effectiveness and high coverage. This work establishes a reusable and scalable verification strategy for FPGA-based CNN accelerators in edge AI deployments, emphasizing the importance of robust hardware validation.