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This paper describes a measurement system for mixed-signal accelerators integrating SRAM compute cells. The system is composed of a cascade of blocks, including a MATLAB control software running on a PC, an FPGA to interact with the accelerator circuit, and dedicated peripherals, integrated on the chip. The measurement system supports iterative routines for full memory array and peripheral circuits characterizations. In this paper, we describe the test infrastructure and report the results of the SRAM array characterization. The SRAM compute cells of the accelerator under test show, in measurement, an average current in computation of 565 nA and a normalized standard deviation σ/µ = 6%, in good agreement with SPICE simulations.

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Test System for an SRAM-Based Mixed-Signal Accelerator

  • 会议论文

  • 发表日期：

    2026年

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  • Michele Caselli,
  • Francesco Malena,
  • Andrea Boni

摘要

This paper describes a measurement system for mixed-signal accelerators integrating SRAM compute cells. The system is composed of a cascade of blocks, including a MATLAB control software running on a PC, an FPGA to interact with the accelerator circuit, and dedicated peripherals, integrated on the chip. The measurement system supports iterative routines for full memory array and peripheral circuits characterizations. In this paper, we describe the test infrastructure and report the results of the SRAM array characterization. The SRAM compute cells of the accelerator under test show, in measurement, an average current in computation of 565 nA and a normalized standard deviation σ/µ = 6%, in good agreement with SPICE simulations.