This paper presents a common but useful modified digital clock recovery system that is used in the implementation of a fully FPGA-based SerDes receiver on a Numerically Controlled Oscillator (NCO). It is implemented on an FPGA platform and was specifically designed for Serializer/Deserializer (SerDes) receivers. The motivation is the well-known drawbacks of conventional analog and digital Phase-Locked Loop (PLL) methods [6] and also the tough integration of PLLs on FPGA systems. Despite being the preferred choice for high-speed systems for a long time, PLLs usually encounter challenges with integration, high power consumption, noise sensitivity, and design complexity when striving for fully digital platforms [7]. To overcome these limitations and enhance overall system performance, the proposed NCO-based architecture incorporates three new features. First, a Most Significant Bit (MSB)-based pulse generation technique is used to generate lowjitter square wave clock signals. This technique produces very stable timing references, which are crucial for SerDes applications. Second, the Frequency Control Word (FCW) can be fine-tuned thanks to the architecture, which enhances edge alignment, reduces synchronization errors, and enables accurate frequency adjustment [4]. Third, by combining a Sigma-Delta Digital-to-Analog Converter (DAC) with an Infinite Impulse Response (IIR) low-pass filter, the system expands its applicability to mixed-signal domains. This makes it possible to generate waveforms smoothly and shape noise effectively. Although IIR filters, NCOs, and Sigma-Delta DACs are all well-established concepts, little is known about how to combine them for clock recovery in high-speed SerDes [8]. The design generates accurate, scalable, and stable clock generation, offering a dependable digital alternative to contemporary high-speed communication systems, as confirmed by simulation and FPGA hardware testing.