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This paper presents the design, implementation, and verification of a Universal Asynchronous Receiver Transmitter (UART) using Verilog with an APB (Advanced Peripheral Bus) Slave Interface. The UART module supports configurable parameters such as data length, parity, stop bits, and baud rate, which are controlled through an internal Control and Status Register (CSR). The transmitter (TX) sends data serially, holding each bit for 16 clock cycles to support 16x oversampling, and always transmits the least significant bit (LSB) first. The receiver (RX) samples incoming data at the middle of the bit period to ensure accurate data capture. The APB slave allows the master to configure the CSR and read status or received data. The status register includes UART states like TX busy, RX busy, frame error, and parity error. Data is only transmitted once per load, and the system waits for new data before initiating another transmission. Testbench (acts as APB Master) simulations validate the UART’s functionality (at a 75 MHz input clock & 9600 bps baud rate), confirming correct APB operations, transmission stability, mid-bit RX sampling, and accurate error detection.

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Design, Implementation and Verification of UART with APB Slave Interface Using Verilog

  • 会议论文

  • 发表日期：

    2026年

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  • Govindchandra Patel,
  • Rahul Gandhi,
  • Atul Baghel,
  • Bhavesh Soni

摘要

This paper presents the design, implementation, and verification of a Universal Asynchronous Receiver Transmitter (UART) using Verilog with an APB (Advanced Peripheral Bus) Slave Interface. The UART module supports configurable parameters such as data length, parity, stop bits, and baud rate, which are controlled through an internal Control and Status Register (CSR). The transmitter (TX) sends data serially, holding each bit for 16 clock cycles to support 16x oversampling, and always transmits the least significant bit (LSB) first. The receiver (RX) samples incoming data at the middle of the bit period to ensure accurate data capture. The APB slave allows the master to configure the CSR and read status or received data. The status register includes UART states like TX busy, RX busy, frame error, and parity error. Data is only transmitted once per load, and the system waits for new data before initiating another transmission. Testbench (acts as APB Master) simulations validate the UART’s functionality (at a 75 MHz input clock & 9600 bps baud rate), confirming correct APB operations, transmission stability, mid-bit RX sampling, and accurate error detection.