The growing integration of embedded cryptographic systems in smart city infrastructure, from connected traffic sensors to smart grids, has heightened the threat of stealthy Hardware Trojans. Lightweight block ciphers, favored for efficiency in such resource-constrained devices, remain susceptible to malicious modification during early design stages. This paper explores Register Transfer Level (RTL)-level Hardware Trojan design and detection through the insertion of nine lightweight Trojans into a Field Programmable Gate Array (FPGA) implementation of the PRESENT lightweight block cipher. The Trojans employ diverse triggering mechanisms based on internal and external system conditions, with payloads ranging from data corruption and information leakage to Denial of Service (DoS) attacks. A Functional Analysis (FA)-based detection method is applied using pseudorandom inputs at the logic simulation level, treating the system as a black-box. Results show that even RTL Trojans with very low triggering probabilities can be detected, albeit with increased simulation time. Hardware overhead remains minimal, with Look-Up Table (LUT) usage rising by just 0.24% to 1.31%.