This paper presents the design and implementation of a System on Chip (SoC) for EEG signal processing using Field Programmable Gate Array (FPGA) technology. The proposed SoC is developed to efficiently perform real-time filtering and feature extraction from raw EEG signals, which are often corrupted by various artifacts. The system architecture includes up-sampling, low pass filtering, high pass filtering, derivative operation, squaring, moving average filtering, down-sampling, and autoregressive (AR) modeling for feature extraction. The design is implemented using Verilog HDL and synthesized on the ALTRA Cyclone DE II FPGA board via Quartus Prime 17.1 Lite Edition. Simulation results using the ISim simulator validate the functional accuracy of each processing block, and performance evaluation confirms low power consumption, optimized timing characteristics, and efficient resource utilization. This SoC design offers a promising solution for real-time biomedical signal processing, with potential for future integration into Brain-Computer Interface (BCI) systems and advanced diagnostic tools.