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This paper presents the design and characterization of the DARE22G Phase-Locked Loop (PLL) for space applications, targeting low period jitter and radiation hardness. Implemented in 22 nm FD-SOI technology with a ring oscillator-based VCO, the PLL achieves sub-1ps normalized period jitter and wide output frequency range (1.953 MHz to 3 GHz). Measurement results across 30 configurations confirm the PLL’s intrinsic jitter stability, with supply noise effects mitigated through normalization. The DARE22G PLL demonstrates suitability for digital systems requiring robust and precise clock generation.

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Jitter Measurement Results of DARE22G Phase-Locked Loop

  • 会议论文

  • 发表日期：

    2026年

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  • SinNyoung Kim,
  • Ian Thomson,
  • Ilker Eryilmaz,
  • Laurent Berti

摘要

This paper presents the design and characterization of the DARE22G Phase-Locked Loop (PLL) for space applications, targeting low period jitter and radiation hardness. Implemented in 22 nm FD-SOI technology with a ring oscillator-based VCO, the PLL achieves sub-1ps normalized period jitter and wide output frequency range (1.953 MHz to 3 GHz). Measurement results across 30 configurations confirm the PLL’s intrinsic jitter stability, with supply noise effects mitigated through normalization. The DARE22G PLL demonstrates suitability for digital systems requiring robust and precise clock generation.