In this research, a 16-transistor Full Adder (FA) CMOS circuit is used to build 4-bit ripple carry adders. The proposed design has less delay and low power consumption. The adder circuits are developed using CMOS technology, which provides effective performance. The implementation of Cadence Virtuoso at 90nm technology uses a 1.8V supply voltage. Performance metrics, including power consumption, delay and Power Delay Product (PDP), are compared with conventional adder designs, and conclusions are drawn on which design provides the best efficiency. In present method, for FA the average power consumption, delay and PDP are reduced by 7.73%, 13.25% and 19.96% respectively. The important parameter for estimating the circuit performance is the PDP. This design has an emphasis on low power consumption, minimum space, and reduced delay, all of which are in keeping with the main goal of VLSI research. The total performance of the digital system is directly impacted by the ripple carry adder's efficiency.