Recent advancements in qubit manipulation in quantum dot arrays, as well as in the classical/quantum co-integration of FD-SOI spin-based quantum circuits shed light on an industrialization path for large-scale quantum computing. We present this path to designing and engineering good qubits using technology that is as close as possible to the most advanced industrial FD-SOI nodes. We then investigate qubit design accounting for the constraints arising from the established industrial fabrication process. More precisely, we repurpose the W vias and, in a single contact patterning step, define the gates that enable to define the electrochemical potential of quantum dots (QDs), as well as the W vias that control the coupling barriers between adjacent QDs. We present simulation-based and experimental results on the individual coupling control of QDs in arrays fabricated on the industrial 28 nm FD-SOI technology. We present detailed wafer-level transfer characteristics of each barrier implemented on a 1x3 linear array at room temperature and at 2K. These results demonstrate that the vias behave like MOSFET gates, providing effective electrostatic control over the silicon channel. This validates the compatibility of the 28 nm FD-SOI industrial route with essential requirements for demonstrating a two-qubit gate.