Quantum arithmetic computation requires a substantial number of scratch qubits to stay reversible. These operations necessitate qubit and gate resources equivalent to those needed for the larger of the input or output registers due to state encoding. Quantum Hamiltonian Computing (QHC) introduces a novel approach by encoding input for logic operations within a single rotating quantum gate. This innovation reduces the required qubit register \( N \) to the size of the output states \( O \) , where \( N = \log _2 O \) . Leveraging QHC principles, we present reversible half-adder and full-adder circuits that compress the standard Toffoli + CNOT layout [Vedral et al., PRA, 54, 11, (1996)] from three-qubit and four-qubit formats for the Quantum half-adder circuit and five sequential Fredkin gates using five qubits [Moutinho et al., PRX Energy 2, 033002 (2023)] into a two-qubit, 4 \(\times \) 4 Hilbert space. This scheme, presented here, is optimized for classical logic evaluated on quantum hardware, which due to unitary evolution can bypass classical CMOS energy limitations to a certain degree. While the present circuits target classical Boolean inputs (i.e., classically controlled operation) and prepare the outputs from the initialized state \(|00\rangle \) , we make this scope explicit: the blocks here are not intended as coherent adders acting on superpositions. Instead, they are resource-minimal classical-to-quantum primitives that realize full truth tables on two qubits with no scratch registers. Because the input parameters are binary, the resulting unitaries reduce to a finite set of two-qubit permutations that can be implemented exactly without T gates or approximation overhead. We further position these blocks as building units for FPGA-like quantum-configurable logic, e.g., programmable interferometer meshes or analog control blocks, where minimizing qubits and circuit depth is advantageous.