In the era of transformative technologies such as artificial intelligence, IoT and big data, the imperative for energy-efficient and high-speed computation in edge devices has become a pivotal concern. However, the conventional von-Neumann architecture is approaching its scalability and power consumption limits. In-memory computing (IMC) emerges as a promising paradigm to address this limitation. This work introduces a 4T SRAM-based IMC SRAM macro featuring separated bit lines, circumventing read disturb issues and enabling bit-parallel computing. Beyond standard read and write operations, this work incorporates additional functionalities like addition, subtraction, multiplication, and more. The proposed SRAM macro undergoes validation using the SMIC 180 nm technology PDK. Post-layout simulation reveals potentials savings of up to 23.72% in area (for a 256 × 64 array) and a reduction in single-cycle latency ranging from 16.3% to 33% compared to 6T SRAM-based alternative. Furthermore, at cryogenic temperature, 4T SRAM exhibits adequate static noise margin (SNM). In comparison to 300 K conditions, the 4T load-less SRAM and 4T driver-less SRAM achieves hold static noise margin (HSNM) improvements of 516%, 40.9% and read static noise margin (RSNM) enhancements of 7.1%, 12.9%, respectively. This positions it as a promising candidate for cryogenic in-memory computing applications.