The Universal Asynchronous Receiver Transmitter (UART) is a serial communication protocol that functions as an integrated circuit, enabling asynchronous data transmission and reception through a computer's serial port. It handles data in bytes, transmitting individual bits in sequence, which are then reconstructed into complete bytes at the receiving end. This study focuses on the design and implementation of UART for RF-based modules using various FPGA technologies, which include components such as a transmitter, receiver, and baud rate generator. The UART protocol is increasingly favored in RF-microcontroller modules for interfacing with other hardware due to its cost-effectiveness and efficiency in short-distance, low-speed data transmission. The streamlined UART_TX comprises a FIFO buffer referred to as ‘bbfifo_16 × 8’ and the compact UART transmitter module ‘quart_tx’. The FIFO buffer is designed to accept byte data for transmission, while the output from the FIFO is controlled by the ‘quart_tx’ transmitter. This circuit automatically fetches data from the buffer to transmit it over the serial line. As depicted in Fig. 4, the UART_TX module includes multiple input and output ports. The ports on UART_TX will connect with the ports on the Spartan 3E. The Serial_out port will link to the rs232_dce_txd port via the tx signal, establishing that serial_out equals rs232_dce_txd. Furthermore, the btn_south port will be connected to reset the buffer. UART_RX consists of a FIFO buffer known as ‘bbfifo_16 × 8’ and the compact UART receiver module ‘quart_rx’. The FIFO buffer is used to store incoming data, with the input side managed by the ‘quart_rx’ receiver. As shown in Fig. 5, the UART_RX module features multiple input and output ports. The ports on UART_RX will interface with the ports on the Spartan 3E. The Serial_in port will connect to the rs232_dce_rxd port via the rx signal, establishing that serial_in equals rs232_dce_rxd. Additionally, the btn_south port will be linked accordingly.