Signals are converted, processed and transmitted digitally exploiting the limitations of, approximating their speech, image and videos but the real world is analog. Interfacing analog and digital systems is necessary to fully leverage the power of digital computation. Design of power-efficient, high sampling rate, noise resistant analog to digital converters (ADCs) remains a significant hurdle in analog circuit design. This paper offers a ready reference to researchers investigating recent developments in time interleaved successive approximation register (TI-SAR) ADC circuit design. After analysing more than 20 publications, important and novel aspects of the circuits were extracted and succinctly presented. The purpose of the paper is to address the dearth of thorough review articles about developments in the design of time-interleaved SAR ADC circuits. The paper addresses the difficulties in designing high speed TI-SAR ADCs in addition to circuit level innovations. The bottlenecks in terms of speed are the effects of mismatch, calibration problems, and settling time reduction. Along with a quantitative analysis of numerous parameters, a summary of the problems and potential solutions has been provided, combining methods from several papers. ADC performance metrics like sampling rate, power consumption, area, SNDR (signal to noise and distortion ratio), figure of merit, and process.