RISC-V is widely used for edge AI acceleration, but most existing processors rely on scalar architectures, resulting in low PE density, inefficient bandwidth utilization, and complicated parallel processing schemes. Traditional Dot-Product (Dot-P) instruction extensions only support four 8-bit MAC operations per cycle, the computational density cannot support neural network implementation. Moreover, the general-purpose register constraint in RISC-V strictly limits matrix kernel dimensions, degrading computational resource utilization. Current multicore solutions require Tightly Coupled Data Memory (TCDM) with doubled core numbers of memory banks, along with mandatory padding operations to prevent bank conflicts, increasing memory subsystem complexity and area overhead. To address these challenges, we propose NNia-8, an 8-core RISC-V processor with six custom instructions for neural network inference acceleration (NNia). By replacing Dot-P operations with Out-Product (Out-P) computation paradigms, we achieve enhanced PE density optimization. Through implicit register invocation techniques integrating computation and memory access operations, along with dedicated buffer enhancements, bandwidth utilization and PE efficiency are substantially improved. Evaluated under the CMOS 55 nm process, NNia-8 achieves 49.9 GOPS at 8-bit precision with energy efficiency reaching 322 GOPS/W, outperforming state-of-the-art solutions.