Big data and AI applications pose significant challenges to traditional distributed shared memory architectures, where network bandwidth and latency constraints have become critical bottlenecks. Although the Compute Express Link (CXL) protocol promises low-latency, high-bandwidth interconnects for memory expansion, existing CXL 1.1 devices still cannot support fine-grained memory sharing across multiple nodes. This paper proposes an FPGA-based distributed shared memory architecture supporting the CXL 2.0+ specification. It features three key innovations for transparent cross-node memory accesses: 1) replacing conventional network stacks with CXL physical links to mitigate the performance overhead of frequent data copying; 2) a hardware-managed memory controller with interleaved access mechanisms to optimize the bandwidth utilization of the CXL-DDR channel; 3) hierarchical queues to ensure memory access orders under high concurrency. This fine-grained memory sharing architecture supports zero-copy data swapping across multiple servers via a pass-by-reference manner. Experimental results show that the end-to-end access latency of our CXL-based shared memory architecture is as low as \(1.25\,\upmu \text {s}\) , 5 \(\times \) lower than that of one-sided Remote Direct Memory Access (RDMA).