Static Random Access Memories (SRAM) are fast and efficient circuits used as the main working memory of processing units. However, associating these volatile memories with external non-volatile memories leads to energy consumption and area penalties, while leading to security issues. Ferroelectric-based NVSRAMs are one of the most promising ways of combining the high efficiency of SRAMs with nonvolatile operations to tackle these challenges. In this work, several design parameters of the bitcell are optimized to ensure error-less data transfer between 6T SRAM internal nodes and ferroelectric capacitors (4C). We present a first detailed study in 130 nm bulk technology then we explore the scalability of this design in a thinner 22 nm FDSOI technology. These NVSRAM circuits presents STORE and RECALL energies ranging from 3fJ/bit to 200fJ/bit. A high reliability is achieved on both technology nodes from −40 °C to +85 °C for SS, TT and FF fabrication corners. We quantify the area overhead as well as the time and energy increases in SRAM operations resulting from the integration of FeCAPs into the bitcell. A previously developed Fast-Erase design technique has also been integrated for countering cold-boot attacks and improving the RECALL operation. Combining design optimizations and Fast-Erase technique enables error-less RECALL while permitting WRITE operations into SRAM part between STORE and RECALL, leading to new applications for NVSRAM circuits.