This paper presents a novel low-power and wide-range phase interpolation-based delay line implemented in 12 nm FinFET technology. The proposed architecture to the best of our knowledge is the most efficient delay line in terms of power consumption, area and linearity in advanced technology nodes due to low complexity and complete controllability over delay range, resolution and operating frequency. The analysis in this paper shows that the input slew rate significantly affects the linearity of the delay line. Consequently, a linearity improvement technique is proposed to control the slew rate, which significantly improves the linearity of the delay line over a wide frequency range. To evaluate the performance of the proposed phase interpolation-based delay line, two common fine delay line architectures including RC delay using binary-weighted capacitors and variable driving strength buffer were designed and simulated in 12 nm FinFET technology to compare with this work. The simulation results demonstrate that the proposed delay line achieves a 30% decrease in power consumption and a 25% reduction in area compared to the RC delay line. In addition, the differential nonlinearity (DNL) values for the variable driving strength buffers range from −1.52 LSB to 3.56 LSB while this work shows significant improvement in terms of linearity with DNL variations of only −0.22 LSB to 0.17 LSB. The proposed delay line consumes 0.56 mW at 5 GHz operating frequency and 0.8 V supply voltage, surpassing other previous studies.