Testing is an essential part of the integrated circuit (IC) manufacturing process to ensure that each produced IC meets its expected standards of functionality, speed, tolerance, power consumption, heat dissipation, etc., and is free of defects. It involves multiple procedures including so-called Structural Testing (ST). The goal of ST is to identify the presence of physical defects as well as potential design problems. During it, special digital patterns (test sets) are applied to primary inputs of the IC under test while its output sets are collected and examined. The input and expected output sets are developed during the IC design stage by using the Automatic Test Pattern Generation (ATPG) process. It is based on formal algorithms for which fault models are employed. Stuck-at faults are among the most fundamental and useful models employed in ATPG. Their utilisation leads to the systemic development of structural test sets capable of identifying and isolating large classes of physical defects in the tested ICs. This paper presents a simple low-cost desktop trainer for teaching the foundations of ST for digital circuits. It is based on the use of two National Instruments (NI) platforms: the NI Educational Laboratory Virtual Instrumentation Suite II (ELVIS) hardware and the NI Laboratory Virtual Instrument Engineering Workbench (LabVIEW) – a software system design and development environment for a visual programming language. The trainer is a new addition to the set of systems for engineering education in electronic test technology that was supported by the IEEE Instrumentation and Measurement Society Course Development Award.