Conflict-based side-channel attacks allow attackers to monitor victims’ access patterns by asserting malicious cache conflicts. While cache randomization has emerged as a potential defense, existing solutions face critical limitations. CEASER-S and DT4+EV10 fail to fully prevent existing eviction set searching algorithms. MIRAGE suffers from intolerable area and power overheads. Chameleon’s relocation mechanism faces the problem of excessive power/energy consumption. To alleviate these limitations, we employ a dual-mapping randomized cache with global indirect replacement (GIR-Cache). A randomized direct-mapped look up table is designed to eliminate dual-index checking overhead by maintaining the active mapping state of each LLC address. Our approach effectively mitigates conflict-based side-channel attacks while incurs negligible runtime performance impact with moderate area and power overhead.

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GIR-Cache: Mitigating Conflict-Based Cache Side-Channel Attacks via Global Indirect Replacement

  • Hao Ma,
  • Zhidong Wang,
  • Da Xie,
  • Ciyan Ouyang,
  • Wei Song

摘要

Conflict-based side-channel attacks allow attackers to monitor victims’ access patterns by asserting malicious cache conflicts. While cache randomization has emerged as a potential defense, existing solutions face critical limitations. CEASER-S and DT4+EV10 fail to fully prevent existing eviction set searching algorithms. MIRAGE suffers from intolerable area and power overheads. Chameleon’s relocation mechanism faces the problem of excessive power/energy consumption. To alleviate these limitations, we employ a dual-mapping randomized cache with global indirect replacement (GIR-Cache). A randomized direct-mapped look up table is designed to eliminate dual-index checking overhead by maintaining the active mapping state of each LLC address. Our approach effectively mitigates conflict-based side-channel attacks while incurs negligible runtime performance impact with moderate area and power overhead.