We conduct a detailed performance comparison of state-of-the-art commercial-off-the-shelf (COTS) RISC-V processors, equipped with single-instruction multiple-data (SIMD) units, using the general matrix-matrix multiplication (GEMM). To address the differences in the implementation of the RISC-V ISA (instruction set architecture) in general, and its RVV vector extension in particular, we use Exo as a tool to accelerate the development of a complete family of micro-kernels that take into account the different characteristics of the architectures and facilitate the generation of highly optimized realizations of GEMM. We show that, since the specific optimizations differ between targets (even if they are under the same RVV umbrella), automatic generation and analytical models are essential tools to identify the optimal realizations.