The increasing resolution of modern sensors results in significant data volumes and overwhelming communication links between images and back-end processors in embedded systems or the cloud. Event cameras mitigate this issue by reducing image data volume, thereby alleviating the pressure, but they necessitate the back-end processor to reconstruct the original image. We propose an advanced event camera system that integrates inference within the sensor itself, using an event-based mechanism to compute relevant pixels for knowledge inference. This pixel processing unit features a dual-channel filter with a Spatial Saliency Generator Unit (SSU), a Temporal Saliency Generator Unit (TSU), and a Saliency Integrating Unit (SIU), which determine salient pixels from current and previous frames. Compared to HARP [6], the FPGA implementation of this architecture significantly enhances computing efficiency and hardware utilization, achieving a 94.55% reduction in LUT usage, a 99.39% reduction in Flip-Flop usage, and a 29.63% reduction in BRAM usage.