This paper gives a comparative study of the K-means clustering algorithm run on three platforms: a CPU, an FPGA, and a hybrid CPU-FPGA setup, focusing on execution efficiency and scalability. The CPU version is suitable for small datasets due to its simple serial processing ability, while the FPGA shows superior performance for larger datasets with hardware acceleration and parallel processing. The hybrid setup employs the ARM Cortex-A9 processor in addition to the programmable logic of the Xilinx ZedBoard (ZYNQ-7000 SoC). The algorithm is run through Vitis on the CPU, while AXI-interfaced IP cores, developed using Vivado, provide signal monitoring and real-time debugging through the Integrated Logic Analyzer (ILA). This setup provides dynamic software control and high-speed processing. The FPGA showed an execution time of 38.077 ns, compared to the 0.015519 s on the CPU, providing a speedup of about 106 times. Implementation issues, such as the lack of native floating-point support and reliance on fixed-point approximations, have been noted for future improvement. Additionally, 8-bit binary representations of centroids are visualized using LEDs on the FPGA, providing a physical and intuitive visualization of the clustering process. This paper illustrates the effectiveness of FPGAs and hybrid CPU-FPGA setups in accelerating compute-intensive machine learning algorithms and the benefits of hardware-based optimization in real-time and embedded systems.