Scholarlink

Control of functional blocks of systems on a chip and application-specific integrated circuits are discussed. Implementation of a configurable 32-bit microprocessor based on RISC-V instruction set architecture for embedded applications and integration into systems on a chip is presented. The processor has 5-stage instruction pipeline. Branch predictors, bypass, hardware integer multiplication and division, as well as instruction cache can be added as options. Capability to flexibly configure the processor core depending on the tasks and limitations imposed on the developed chip is demonstrated. Performance and power consumption indicators of various processor core configurations are defined. One of the microprocessor configurations with RV32IMC instruction set, branch predictors, bypass, as well as hardware integer multiplication and division was implemented in CMOS SOI 0.6 µm technology using the Cadence EDA Tools. The physical implementation results in a circuit of 23.99 mm2. The chip contains over 8,000 digital elements including 2350 D-triggers. The circuit consists of 70% digital elements. The microprocessor successfully passed RISC-V architecture compatibility tests. The results of the CoreMark benchmark for various microprocessor configurations are also presented.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Designing a Configurable 32-Bit Microprocessor Based on RISC-V Architecture for Specialized Applications

  • 会议论文

  • 发表日期：

    2026年

查看全文
  • Sergey A. Kornev,
  • Vladimir V. Andreev,
  • Alexander A. Stolyarov

摘要

Control of functional blocks of systems on a chip and application-specific integrated circuits are discussed. Implementation of a configurable 32-bit microprocessor based on RISC-V instruction set architecture for embedded applications and integration into systems on a chip is presented. The processor has 5-stage instruction pipeline. Branch predictors, bypass, hardware integer multiplication and division, as well as instruction cache can be added as options. Capability to flexibly configure the processor core depending on the tasks and limitations imposed on the developed chip is demonstrated. Performance and power consumption indicators of various processor core configurations are defined. One of the microprocessor configurations with RV32IMC instruction set, branch predictors, bypass, as well as hardware integer multiplication and division was implemented in CMOS SOI 0.6 µm technology using the Cadence EDA Tools. The physical implementation results in a circuit of 23.99 mm2. The chip contains over 8,000 digital elements including 2350 D-triggers. The circuit consists of 70% digital elements. The microprocessor successfully passed RISC-V architecture compatibility tests. The results of the CoreMark benchmark for various microprocessor configurations are also presented.