The demand for secure image transmission leads to reversible logic-based encryption as an attractive solution because it provides low-power performance and maintains computation accuracy. An FPGA-based image encryption system that utilizes Reversible Logic-based Cryptographic Design (RLCD) enables high security operations with minimal energy expenditure. The system uses Verilog HDL to develop its design which runs through Xilinx Vivado to perform encryption in 3.85 ms indicating its readiness for real-time usage. The proposed work establishes itself as the most energy-efficient method since it consumes only 2.8 W. The encryption algorithm proved its strength through experimental testing which produced uniform intensity distribution based on histogram analysis and reduced adjacent pixel dependency outcomes from correlation coefficient analysis. The proposed method delivers better security and hardware efficiency than standard cryptographic methods which makes it suitable for resource-limited secure image processing systems.