At present, various models of neurons oriented at implementation in the digital element basis are known, but these models have significant differences from real biological neurons, which operate not with code combinations in binary representation, but with impulse streams. The author offers a variant of realization of the neural cell models; the “biological nature” of these models is manifested in the use of bit streams to represent information. Computational processing of streams occurs in a continuous tracking mode without conversion into traditional binary codes. In the article the digital element base for design of bit-stream modules represented by logic primitives and digital modules is shown; the generalized variant of one-layer bit-stream perceptron is considered; the possibility of implementation of the proposed technical solutions on the basis of FPGA is illustrated. The developed modules are written in the SystemVerilog language, it allows to implement them in FPGAs of different manufacturers and use them as a basis for further design of ASIC implementations.

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Bit-Stream Perceptron

  • Olga I. Bureneva

摘要

At present, various models of neurons oriented at implementation in the digital element basis are known, but these models have significant differences from real biological neurons, which operate not with code combinations in binary representation, but with impulse streams. The author offers a variant of realization of the neural cell models; the “biological nature” of these models is manifested in the use of bit streams to represent information. Computational processing of streams occurs in a continuous tracking mode without conversion into traditional binary codes. In the article the digital element base for design of bit-stream modules represented by logic primitives and digital modules is shown; the generalized variant of one-layer bit-stream perceptron is considered; the possibility of implementation of the proposed technical solutions on the basis of FPGA is illustrated. The developed modules are written in the SystemVerilog language, it allows to implement them in FPGAs of different manufacturers and use them as a basis for further design of ASIC implementations.