Semi-structured data formats, such as JSON, are widely adopted in big data applications to achieve flexibility, fast integration and portability. As these formats are commonly highly sparse, compression is often applied before data is stored or transmitted over networks. However, since semi-structured records often need to be accessed individually, they need to be compressed separately, resulting in low compression factors when applying traditional Lempel-Ziv compression schemes. As a remedy, Fast Static Symbol Table (FSST) was proposed, a lightweight dictionary-based compression scheme specifically designed for short strings. In this paper, we present hardware acceleration techniques for the FSST compression scheme. Moreover, we evaluate the applicability of FSST to semi-structured data, such as JSON, and compare it to other compression schemes. Finally, in the evaluation of the presented accelerator circuits, we report speedups of 1.4 to 2.6 times and a reduction in energy consumption of 6.0 to 10.5 times compared to the open source FSST software implementation.

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FSST Compression of JSON Data on FPGAs

  • Tobias Hahn,
  • Jan Hofmann,
  • Stefan Wildermann,
  • Jürgen Teich

摘要

Semi-structured data formats, such as JSON, are widely adopted in big data applications to achieve flexibility, fast integration and portability. As these formats are commonly highly sparse, compression is often applied before data is stored or transmitted over networks. However, since semi-structured records often need to be accessed individually, they need to be compressed separately, resulting in low compression factors when applying traditional Lempel-Ziv compression schemes. As a remedy, Fast Static Symbol Table (FSST) was proposed, a lightweight dictionary-based compression scheme specifically designed for short strings. In this paper, we present hardware acceleration techniques for the FSST compression scheme. Moreover, we evaluate the applicability of FSST to semi-structured data, such as JSON, and compare it to other compression schemes. Finally, in the evaluation of the presented accelerator circuits, we report speedups of 1.4 to 2.6 times and a reduction in energy consumption of 6.0 to 10.5 times compared to the open source FSST software implementation.