OpenVADL is an open source implementation of the Vienna Architecture Description Language (VADL). VADL is a processor description language (PDL) that enables the concise formal specification of processor architectures. OpenVADL automatically generates an assembler, an LLVM based compiler and a QEMU based instruction set simulator from a single VADL processor specification. Automatic generation of synthesizable specifications in a hardware description language is under development. VADL strictly separates the instruction set architecture (ISA) specification from the microarchitecture (MiA) specification. VADL’s MiA specification operates at a higher level of abstraction compared to existing PDLs. This article introduces OpenVADL, describes the generator techniques in detail and shows the performance of the generators in an empirical evaluation. The evaluation demonstrates the capabilities of OpenVADL and its efficiency. An OpenVADL generated instruction set simulator is up to 77% faster than the official human written QEMU frontend for the RISC-V RV64IM instruction set architecture.