Trustworthy embedded systems are essential for ensuring security and reliability in modern System-on-Chip (SoC) architectures. This paper explores hardware and software implementations of a monitoring unit that classifies bus transactions using decision tree algorithms to detect anomalies in real time. The hardware implementation achieves low latency and high throughput, while the software approach provides greater flexibility and scalability on manycore platforms. Experimental results demonstrate significant improvements in detection accuracy and system performance, offering valuable insights into the trade-offs between performance and adaptability in embedded system design. In the analyzed scenario, the hardware implementation achieves one classification per cycle with 13–26 cycles latency, while the manycore solution can be scaled to up to 32 cores. The dedicated hardware implementation can reach a maximum operational frequency of 200–333 MHz on an Xilinx Virtex-7 FPGA, while the CoreVA CPU runs at 100 MHz.