This paper focuses on implementing a binary neural associative memory (BINAM) using high-bandwidth memory (HBM) using modern FPGA technology. The target platform for this implementation is the AMD/Xilinx VCU128 evaluation kit, which is based on an UltraScale+ FPGA and provides 8 GB of high-bandwidth memory. The implementation was carried out using high-level synthesis (HLS). For the learning component of the BINAM, two different approaches for learning sparsely coded data were evaluated: one with single accesses and the other with burst row accesses. Additionally, the overall performance was assessed when varying the number of processing elements (PEs) that can operate in parallel due to the segmented architecture. Various designs with neuron counts ranging from 8,192 to 253,440, alongside different numbers of parallel working PEs, were generated to evaluate performance. Each design was tested with one million sparse vectors. The maximum measured performance for learning was between 271,400 and 764,111 operations per second (OP/s), depending on the size of the BINAM. For association, a maximum of 170,005 to 567,956 OP/s was measured. Compared to a previously published BINAM architecture on a similar FPGA that used DDR4 memory for storing the weight matrix, our implementation achieved speedups of up to 4.43 times for learning the weight matrix and 1.8 times for data retrieval by association.