Hardware Fault injection can leave processors in weird micro-architecture states that evade detection by conventional software-level monitors, jeopardizing system reliability. We propose \(\mu \) Scan, a deep learning framework that leverages scan-chain observability to detect such anomalous states. \(\mu \) Scan fine-tunes a large language model (LLM) to classify single-cycle processor states as weird or sane, achieving an average classification accuracy of 92% and maintaining robust performance across different CPU architectures (MSP430, PICO (RV32IC), IBEX (RV32IMC)). We further refine this LLM classifier with reinforcement learning, which sharpens its decision boundaries and improves detection of borderline anomalies. \(\mu \) Scan also employs a graph neural network (GNN) to analyze multi-cycle fault patterns, capturing complex temporal dependencies that single-cycle analysis might miss. This GNN-based analysis successfully identifies recurring fault sequences and maps them to known Common Weakness Enumeration (CWE) vulnerability classes, revealing potential hardware design flaws. \(\mu \) Scan demonstrates scalability and generalization on multiple processor architectures (including micro-coded and pipelined cores) and is evaluated with both pre-silicon simulation data and a post-silicon prototype. Our results show that \(\mu \) Scan enables early detection of micro-architecture vulnerabilities in the design phase and provides a robust post-silicon anomaly detection mechanism.