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With the continued scaling of CMOS technology, multiple-bit upsets (MBU) pose a growing threat to the reliability of SRAM-FPGA. While radiation testing remains the primary method for MBU analysis, it requires specialized test facilities. Emulated fault injection offers a cost-effective alternative but current approaches depend on prior radiation data or proprietary layout information. In this work, we investigate the feasibility of multiple-bit fault emulation using Long Short-term Memory (LSTM) network. The LSTM model processes fault sequences using frame hierarchy to identify critical state transitions and thereby predict failure-inducing bit combinations. Evaluations on AES and CORDIC implementations demonstrate an average f1 score of 88%. The key contributions include: (1) a framework to model multiple-bit dependencies using only frame address information, (2) an LSTM architecture that reduces the campaign duration by 40% with just 3.5% timing overhead, and (3) an efficient fault injection methodology that detects 98% of multiple-bit failures. Our approach complements radiation testing by providing a practical solution for early-stage design validation, enabling faster FPGA reliability assessments.

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Exploring the Potential of LSTM On Emulating Multiple-bit Fault Injection in SRAM-FPGA

  • 会议论文

  • 发表日期：

    2026年

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  • Trishna Rajkumar,
  • Johnny Öberg

摘要

With the continued scaling of CMOS technology, multiple-bit upsets (MBU) pose a growing threat to the reliability of SRAM-FPGA. While radiation testing remains the primary method for MBU analysis, it requires specialized test facilities. Emulated fault injection offers a cost-effective alternative but current approaches depend on prior radiation data or proprietary layout information. In this work, we investigate the feasibility of multiple-bit fault emulation using Long Short-term Memory (LSTM) network. The LSTM model processes fault sequences using frame hierarchy to identify critical state transitions and thereby predict failure-inducing bit combinations. Evaluations on AES and CORDIC implementations demonstrate an average f1 score of 88%. The key contributions include: (1) a framework to model multiple-bit dependencies using only frame address information, (2) an LSTM architecture that reduces the campaign duration by 40% with just 3.5% timing overhead, and (3) an efficient fault injection methodology that detects 98% of multiple-bit failures. Our approach complements radiation testing by providing a practical solution for early-stage design validation, enabling faster FPGA reliability assessments.