Safety-critical embedded systems have become a part of everyone’s daily life. Before deploying these systems, their safety must be ensured to prevent severe accidents. A part of the verification process to minimize system failures is a hazard analysis. One such technique is System-Theoretic Process Analysis (STPA), which finds more causes of failures than other hazard analysis techniques. The disadvantage of hazard analyses is that they are time-consuming and prone to human error since they are performed manually. We propose several techniques to ease the STPA process and reduce pitfalls. These encompass automated component generation and consistency checks as well as enhanced utilization of diagrams to provide a good overview and ease the discussion with other stakeholders.