Error-Correcting Codes (ECCs) are essential for achieving fault tolerance in hardware accelerators deployed in safety-critical applications, such as those used to accelerate neural network inference and cryptographic processing. High-Level Synthesis (HLS) enables the automatic translation of ECC models described in C/C++ into synthesisable hardware, but the structure and style of such descriptions significantly affect circuit-level efficiency. This work investigates five ECC coding strategies, each representing a distinct combination of syndrome computation and correction mechanisms. These strategies are implemented using C++ integers or using arbitrary precision integers provided by the HLS AP_INT library. Considered ECC protection levels are Single, Double, and Triple-Adjacent Error Correction for dataword lengths of 8, 16, and 32 bits. This results in a total of 90 ECC configurations synthesised for both ASIC and FPGA targets, yielding 180 hardware implementations in total. Hardware metrics, including area, power consumption, latency, and resource usage, are evaluated and analysed using analysis of variance (ANOVA) to determine the influence of each design factor. Results indicate that logic-oriented descriptions generally yield more efficient circuits for ASICs, whereas memory-centric implementations perform better on FPGAs equipped with dedicated BRAM. The AP_INT library has minimal statistical impact but provides finer control over bit-widths. Based on these findings, a set of high-level modelling guidelines is proposed to guide the efficient high-level implementation of ECCs via HLS.