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The Device Identifier Composition Engine (DICE) is a security architecture proposed by the Trusted Computing Group (TCG), primarily intended for resource-constrained devices. The DICE architecture serves as a basic Root of Trust (RoT) by providing a boot time measurement to generate a unique cryptographic device identity, only leveraging minimal hardware requirements and software techniques. The generated identity can then be used for various purposes, e.g., in a remote attestation process to prove the identity and integrity of the device. In this paper, we extend TCG’s DICE architecture to support additional security mechanisms, such as secure boot, firmware recovery, and secure firmware update, relying on symmetric cryptography only. These additional mechanisms enhance the DICE architecture to meet the National Institute of Standards and Technology (NIST) requirements for firmware resilience by providing protection, detection, and recovery capabilities. To show the feasibility of the proposed extensions, we provide implementation results for an ARM Cortex-M4-based STM32L4R5ZI microcontroller unit (MCU). Our results show that all extensions can be seamlessly integrated into resource-constrained, off-the-shelf devices with a minor overhead regarding code size and boot time.

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A Cyber-Resilient DICE Architecture for Resource-Constrained Devices

  • 会议论文

  • 发表日期：

    2025年

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  • Utku Budak,
  • Malek Safieh,
  • Fabrizio De Santis,
  • Georg Sigl

摘要

The Device Identifier Composition Engine (DICE) is a security architecture proposed by the Trusted Computing Group (TCG), primarily intended for resource-constrained devices. The DICE architecture serves as a basic Root of Trust (RoT) by providing a boot time measurement to generate a unique cryptographic device identity, only leveraging minimal hardware requirements and software techniques. The generated identity can then be used for various purposes, e.g., in a remote attestation process to prove the identity and integrity of the device. In this paper, we extend TCG’s DICE architecture to support additional security mechanisms, such as secure boot, firmware recovery, and secure firmware update, relying on symmetric cryptography only. These additional mechanisms enhance the DICE architecture to meet the National Institute of Standards and Technology (NIST) requirements for firmware resilience by providing protection, detection, and recovery capabilities. To show the feasibility of the proposed extensions, we provide implementation results for an ARM Cortex-M4-based STM32L4R5ZI microcontroller unit (MCU). Our results show that all extensions can be seamlessly integrated into resource-constrained, off-the-shelf devices with a minor overhead regarding code size and boot time.