Efficient multipliers are every much required for high performance computations for signal processing, graphic processing, communication systems etc. Smaller area, high speed, low voltage and lesser power consumptions are the most important required parameters for high performance applications. The paper gives a path or a hierarchy to select a multiplier and its internal hardware i.e. a top-down approach from multiplier circuit to design styles to MOSFET to channel length and supply voltage. The multipliers and adders form the core of data-path in processors. In this paper, they are selected on the basis of processing time and then the adders within the multipliers are designed considering the power dissipation parameter. The same is implemented using microwind and DSCH 3.9 software. The simulation is carried out with 180, 65 and 32 nm technology with varied supply voltage.