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The Coordinate Rotation Digital Computer (CORDIC) algorithm is widely recognized for its fast real-time processing capabilities, making it highly suitable for hardware implementations in diverse applications such as signal processing, high-performance computing, and edge computing devices. Despite its advantages, the traditional CORDIC algorithm’s iterative computational method introduces significant challenges, including a complex structure and high hardware resource consumption, which can limit its efficiency and scalability in certain applications. In this article, we introduce an innovative and efficient variation of the CORDIC algorithm designed to address these challenges. Our proposed algorithm significantly reduces the number of required operations while maintaining computational accuracy, thereby optimizing performance. Furthermore, we demonstrate that this streamlined algorithm can be effectively implemented on Field-Programmable Gate Arrays (FPGAs), leveraging their reconfigurable hardware to achieve enhanced processing speeds and reduced resource utilization. This advancement not only improves the feasibility of using CORDIC in resource-constrained environments but also expands its applicability in modern computing contexts.

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Low Latency Recoding CORDIC Algorithm for FPGA Implementation

  • 会议论文

  • 发表日期：

    2025年

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  • Pawel Poczekajlo,
  • Leonid Moroz,
  • Ewa Deelman,
  • Michela Taufer,
  • Pawel Gepner,
  • Jerzy Krawiec

摘要

The Coordinate Rotation Digital Computer (CORDIC) algorithm is widely recognized for its fast real-time processing capabilities, making it highly suitable for hardware implementations in diverse applications such as signal processing, high-performance computing, and edge computing devices. Despite its advantages, the traditional CORDIC algorithm’s iterative computational method introduces significant challenges, including a complex structure and high hardware resource consumption, which can limit its efficiency and scalability in certain applications. In this article, we introduce an innovative and efficient variation of the CORDIC algorithm designed to address these challenges. Our proposed algorithm significantly reduces the number of required operations while maintaining computational accuracy, thereby optimizing performance. Furthermore, we demonstrate that this streamlined algorithm can be effectively implemented on Field-Programmable Gate Arrays (FPGAs), leveraging their reconfigurable hardware to achieve enhanced processing speeds and reduced resource utilization. This advancement not only improves the feasibility of using CORDIC in resource-constrained environments but also expands its applicability in modern computing contexts.