The previous chapter analyzed the standard level-crossing analog-to-digital converter (LCADC) architecture and found that the topology can offer a significant system-level advantage over classical digital compression. However, at the ADC level, the power consumption of the continuous-time (CT) comparator limits the LCADC power efficiency for higher quantizer resolutions ( \({>}7\) bits). Moreover, once a timer circuit is required to synchronize the asynchronous LCADC output—which is required for applications that have to work in a synchronous fashion—the LCADC power efficiency is further degraded. The timer also increases the output data rate of the LCADC, undoing part of the system-level benefits. To address all these shortcomings, this chapter will present an LCADC topology that uses an adaptive clocking strategy. It overcomes the limitations of previous asynchronous LCADCs by using power-efficient and highly accurate clocked comparators, an on-chip clock generator to generate multiple sample clocks for the ADC to enable adaptive clocking and event logic that dynamically adjusts the instantaneous sample clock of the ADC to the signal activity, limiting the power waste.