This chapter presents the system-level analysis of a pipelined-SAR ADC and determines the optimal bit splitting between the coarse and fine stages of the ADC to achieve optimal power efficiency. Various CDAC switching schemes are also investigated to further minimize the power consumption of the ADC. At ADC resolution higher than 12 bits, mismatch effects limit the ADC linearity and increase the CDAC sampling capacitance, which degrades the sampling frequency. Therefore, a novel mismatch calibration method is proposed to minimize the harmonics caused by mismatch. At the end of this chapter, all sub-blocks with the TID effects and SEEs are analyzed. The TID has a smaller effect on the pipelined-SAR ADC in the 65 nm process thanks to the process scaling. However, for the SEEs, the residual amplifier and some digital circuits, such as the clock generation block, can cause multiple errors or even unrecoverable failure of the ADC outputs. They need to be hardened to increase the overall SEE tolerance.