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Since a 65 nm CMOS technology is used for the development of the radiation-hardened ADC, the technology performance under radiation effects must be evaluated before it is used, especially for SEEs. Therefore, this chapter first discusses the advantages and disadvantages of advanced CMOS technology in terms of radiation effects, cost, and development effort. Then, 65 nm CMOS technology is analyzed and evaluated as a suitable candidate for space project development. A 65 nm test chip to characterize the SET ionization charge and pulse duration was developed and tested under a heavy ion beam. The results of the heavy ion test are very valuable to obtain an accurate SET model for radiation-hardened IC, which is later used in the Radiation Hardened By Design (RHBD) process in ADC.

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Technology Evaulation Design Consideration and a 65-nm CMOS Technology Test Vehicle (Godzilla) for SET Evaluation

  • 章节

  • 发表日期：

    2026年

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  • Zheyi Li,
  • Laurent Berti,
  • Paul Leroux

摘要

Since a 65 nm CMOS technology is used for the development of the radiation-hardened ADC, the technology performance under radiation effects must be evaluated before it is used, especially for SEEs. Therefore, this chapter first discusses the advantages and disadvantages of advanced CMOS technology in terms of radiation effects, cost, and development effort. Then, 65 nm CMOS technology is analyzed and evaluated as a suitable candidate for space project development. A 65 nm test chip to characterize the SET ionization charge and pulse duration was developed and tested under a heavy ion beam. The results of the heavy ion test are very valuable to obtain an accurate SET model for radiation-hardened IC, which is later used in the Radiation Hardened By Design (RHBD) process in ADC.