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This paper leverages the gem5 simulator to analyze a microarchitectural KASLR break on RISC-V systems. Previous research [2] demonstrated the feasibility of KASLR breaks on RISC-V hardware platforms (C906 and U74). Our paper aims to provide insights that are not easily attainable through traditional hardware experiments. By employing gem5, we gain access to fine-grained metrics such as cycle counts, cache behavior, branch prediction statistics, and TLB accesses, among others. These detailed insights give a deeper analysis of the KASLR bypass and help understand the attack mechanics better.

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Evaluating KASLR Break on RISC-V Using Gem5: Microarchitectural Side-Channel Analysis of Page-Table Walks

  • 会议论文

  • 发表日期：

    2025年

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  • Mahreen Khan,
  • Maria Mushtaq,
  • Renaud Pacalet,
  • Ludovic Apvrille

摘要

This paper leverages the gem5 simulator to analyze a microarchitectural KASLR break on RISC-V systems. Previous research [2] demonstrated the feasibility of KASLR breaks on RISC-V hardware platforms (C906 and U74). Our paper aims to provide insights that are not easily attainable through traditional hardware experiments. By employing gem5, we gain access to fine-grained metrics such as cycle counts, cache behavior, branch prediction statistics, and TLB accesses, among others. These detailed insights give a deeper analysis of the KASLR bypass and help understand the attack mechanics better.