The magnitude comparator is a dynamic and important part in developing high speed VLSI circuits for controllers and processors. One of the merits of the Magnitude comparator in developing the high-speed circuits for VLSI mainly depends on critical path delay which depends on the inner difficulty in the circuit. To have advantage over this we need to develop a 2-novel 1-bit comparator circuits and 2-bit comparator circuit by using CMOS logic structures (combination of pass transistor logic (PTL) and transmission gate logic (TGL)). The proposed 1-bit comparator circuits have improved power delay product (PDP) over other existing ones. The Mentor Graphics tool is used to execute the simulation results at VDD = 0.5 V using 45-nm CMOS technology. It includes the design and execution of a 3-bit magnitude comparator designed with 1-bit comparator circuits and 2-bit comparator circuit. The proposed 3-bit comparator circuit when compared to current magnitude comparators, it consumes less power and takes up less space on the silicon chip.