SRAM, also known as static random-access memory, constitutes an essential and crucial storage technology. SRAM exhibits exceptional speed and durability yet encounters design obstacles in Nanoscale CMOS technology, including elevated leakage, power usage, and dependability concerns. Therefore, designers must operate in the sub-micron domain, prioritizing leakage characteristics. This article describes the creation of a 1 KB memory array using CMOS technology. A 1-bit 12T SRAM device and a 1-volt voltage source power the memory array. We have designed an SRAM that features a 32 × 32 SRAM arrangement. Array architecture was established utilizing a 12T SRAM cell, which had a minimal leakage power of 0.021 μW. Array architecture was established utilizing a 12T SRAM cell, which consumed 49.2 μW and 397 μW of power for reading and writing operations, respectively. The 32 × 32 SRAM array demonstrated superior performance in power usage for both writing and reading functions compared to the conventional 8T, 7T, and 6T SRAMs. The Cadence Virtuoso software executed the entire task using CMOS 45 nm technology.