Ternary Content Addressable Memory (TCAM) serves as a critical component in high-performance networking devices, particularly in routing tables, due to its rapid lookup capabilities. However, the widespread use of TCAM introduces challenges, such as considerable power consumption and susceptibility to power analysis (PA) attacks. This study explores a novel approach to address these issues, proposing a TCAM architecture designed to reduce leakage power and enhance security. The security-oriented solution involves the integration of a 7T SRAM cell, featuring an additional transistor compared to the conventional 6T SRAM cells commonly found in TCAM implementations. This design aims to mitigate the vulnerabilities associated with conventional TCAMs when facing side-channel power analysis attacks. To showcase the practical application of this proposed technique, the implementation is conducted in Cadence 45nm technology.