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In our proposed work a 2.4 GHz PLL was designed in 180 nm technology. PLLs were created specifically for transceivers and processors to generate frequencies. The proposed PLL has acquired lock in 600 ns. The reference frequency was taken as 75 MHz. This design made use of a LC type VCO. This paper is unique from the point of view that usually a PLL design is realized using a passive loop filter. But due to the limited range of this filter, this design has employed the use of an active loop filter. An active loop filter has been designed using a Telescopic Opamp with 40 dB gain at lower frequencies. With a higher control range we can lock the VCO at a higher frequency band. The range of the control voltage was 1.6–1.8 V. The phase noise measured was –156 dBc/Hz at 100 MHz offset. The total power dissipation is quite low at 36.84 mW for the entire design.

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A 2.4 GHz PLL Design Using a Source Switched Charge Pump and An Active Loop Filter

  • 会议论文

  • 发表日期：

    2025年

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  • Sayali Pralhad Joshi,
  • Vibha Vyas,
  • Vaishali Ingale,
  • Vanita Agarwal

摘要

In our proposed work a 2.4 GHz PLL was designed in 180 nm technology. PLLs were created specifically for transceivers and processors to generate frequencies. The proposed PLL has acquired lock in 600 ns. The reference frequency was taken as 75 MHz. This design made use of a LC type VCO. This paper is unique from the point of view that usually a PLL design is realized using a passive loop filter. But due to the limited range of this filter, this design has employed the use of an active loop filter. An active loop filter has been designed using a Telescopic Opamp with 40 dB gain at lower frequencies. With a higher control range we can lock the VCO at a higher frequency band. The range of the control voltage was 1.6–1.8 V. The phase noise measured was –156 dBc/Hz at 100 MHz offset. The total power dissipation is quite low at 36.84 mW for the entire design.