In this work a comprehensive performance analysis of a 16-bit RISC processor integrated with two different multiplier architectures namely Vedic multiplier and shift and add multiplier. The objective was to evaluate and compare the efficiency and effectiveness of these multiplier designs in terms of performance and power consumption. The designs were implemented and synthesized using Verilog in Xilinx Vivado. The tested architecture was practically implemented on a Spartan 7 FPGA board and simulated on spartan 7, basys 3 and nexys A7 100T FPGA boards. The above two multipliers were implemented inside a 16-bit RISC processor and the processor performance was measured. The performance was measured using parameters like WNS (Worst Negative Slack), TNS (Total Negative Slack), WHS (Worst Hold Slack), THS (Total Hold Slack), TPWS (Total Pulse Width Slack), Total Power, Number of LUT’s used and Number of Flip Flops used. It is observed that the performance of RISC processor implemented on Spartan 7 FPGA board improves by around 34.89% when a Vedic multiplier is used instead of Shift and Add multiplier.