Static random-access memory (SRAM) is becoming more and more in demand as portable devices become more common. SRAM is also widely used in high-performance VLSI circuits and System on Chips. Given that memory systems account for 60% to 70% of the total chip area, optimizing SRAM has emerged as a pivotal focus of advanced research in semiconductor design. The optimization of the chip’s overall performance may result from the optimization of its performance parameters. To reduce the amount of power dissipated while preserving speed and stability, this study has designed and analyzed 5T, 6T, and 7T SRAM cells at various technologies. Next, power dissipation—that is, dynamic and static power dissipation—and delay are employed to evaluate SRAM cells’ performance.To overcome the relatively high static and total power loss problems that beset the original 6T SRAM cell, a 7T static random-access memory (SRAM) cell was developed. However, this all takes up more space and causes delays. In this study, a 5T SRAM cell under 180 nm, 90 nm, and 45 nm CMOS technology is built and verified by Monte Carlo simulation. Compared to 7T and 6T, the overall power is decreased by 94.2% and 96.6%, respectively. Static power is also reduced by 75.8% and 79.9% in comparison to 7T and 6T, respectively. In comparison to 7T and 6T, the suggested cell’s speed increased by 47.6% and 53.9%, respectively, while maintaining a respectable level of stability.